1. Field of the Invention
The invention relates generally to a method of manufacturing a flash memory cell and, more particularly, to a method of forming a self-aligned floating gate in a flash memory cell.
2. Description of the Prior Art
Generally, a flash memory cell is implemented by means of STI (shallow trench isolation) using a device isolation process. When isolating a floating gate using a mask patterning, wafer uniformity can be very poor due to variation in the critical dimension (CD). It is thus difficult to implement a uniform floating gate. There is also a problem in that program and erase failure of the memory cell, etc., may occur depending on variation in the coupling ratio.
Furthermore, with more highly integrated designs, if it is desired to implement a small space less than 0.15 xcexcm, the mask process is made more difficult. Due to this, it makes difficult a method of manufacturing a flash memory functioning as an important factor in implementing a uniform floating gate. In addition, as the difference in the coupling ratio is increased if the floating gate is not formed uniformly, there is an over erase problem, etc. upon a programming and erasure of the memory cell, adversely affecting the characteristic of a device. Due to an increase in the mask process, the throughput of the product is lowered and the product cost is increased.
Therefore, in a 0.13 xcexcm technology flash memory cell, the mask and etch processes for the floating gate are not implemented. Instead, the floating gate is formed by means of a self-aligned method. In the self-aligned method, however, there occurs a phenomenon by which a moat region is excessively cleaned by isotropic etch performed upon the cleaning process for etching the trench insulating film after STI process (CMP, chemical mechanical polishing). Due to this, the tunnel oxide film is made thin in a subsequent process and the characteristic of the entire device is degraded. Therefore, there is a need to increase the coupling ratio by securing a cell in which a moat does not occur in a highly integrated flash device.
The present invention is designed to solve the above problems. An object of the present invention is to provide a method of manufacturing a flash memory cell capable of optimizing the spacing of a floating gate as well as prohibiting generation of a moat in a trench insulating film, in a way such that an ion implantation process is performed before the cleaning process for etching a protrusion of the trench insulating film as a nipple shape having a given width, in order to increase the etch rate of portions except for a portion where the moat is generated among the protrusion of the trench insulating film.
In order to accomplish the above object, a method of manufacturing a flash memory cell according to the present invention comprises the steps of forming a pad oxide film and a pad nitride film on a semiconductor substrate; forming a trench in the semiconductor substrate; forming a trench insulating film on the entire structure and then performing a first chemical mechanical polishing (CMP) process to isolate the trench insulating film; removing the pad nitride film to expose a protrusion of the trench insulating film; performing an ion implantation process to dope the protrusion of the trench insulating film; performing a cleaning process to etch the protrusion of the trench insulating film by a given width; forming a first polysilicon layer on the entire structure and then performing a second CMP process to form an isolate floating gate; and forming a dielectric film and a second polysilicon layer on the entire structure and then performing a respective etch process to form a control gate.